The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Aug. 27, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Satoshi Kaburaki, Meguro, JP;

Katsuya Ohno, Yokohama, JP;

Hiroshi Katougi, Isehara, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/0891 (2016.01); G06F 12/10 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0611 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G06F 12/0891 (2013.01); G06F 12/10 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/2022 (2013.01);
Abstract

According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to manage a first cache which stores a part of a logical-to-physical address translation table in the nonvolatile memory. The first cache includes cache lines each including sub-lines. Each of entries of a first cache tag includes bitmap flags corresponding to the sub-lines in the corresponding cache line. Each bitmap flag indicates whether data of the logical-to-physical address translation table is already transferred to a corresponding sub-line. The controller determines a cache line including the smallest number of sub-lines to which data of the logical-to-physical address translation table is already transferred, as a cache line to be replaced.


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