The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2020

Filed:

Oct. 01, 2018
Applicant:

Marvell World Trade Ltd., St. Michael, BB;

Inventor:

Thomas Kniplitsch, Insheim, DE;

Assignee:

Marvell World Trade Ltd., St. Michael, BB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); H04L 12/26 (2006.01); G01R 31/3185 (2006.01); G01R 31/319 (2006.01); G06F 11/22 (2006.01); G06F 21/86 (2013.01); H04L 9/32 (2006.01); H04L 12/40 (2006.01);
U.S. Cl.
CPC ...
H04L 43/0817 (2013.01); G01R 31/31907 (2013.01); G01R 31/318533 (2013.01); G01R 31/318597 (2013.01); G06F 11/2294 (2013.01); G06F 21/86 (2013.01); H04L 9/3226 (2013.01); H04L 12/40 (2013.01);
Abstract

A network device is provided and operative to secure remote access to an internal component including a processor and/or a register. The network device includes an Ethernet interface, an access port, and a controller. The Ethernet interface receives, from a host device, frames transmitted over an Ethernet network. The access port is physically connected to the internal component and physically inaccessible to the host device. The controller is physically connected to the access port. The controller: accesses the internal component via the access port; based on the frames, determines whether the host device is authorized; if the host device is not authorized, prevent the host device from accessing the processor or the register; and if the host device is authorized, permit the host device, via the Ethernet interface and the access port, to control operation of the processor or change the contents of the register.


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