The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2020

Filed:

Nov. 09, 2018
Applicant:

Analog Devices, Inc., Norwood, MA (US);

Inventors:

Yoshinori Kusuda, San Jose, CA (US);

Gustavo Castro, North Andover, MA (US);

Scott Andrew Hunt, Arlington, MA (US);

Sean Patrick Kowalik, Chelmsford, MA (US);

Simon Nicholas Fiedler Basilico, San Francisco, CA (US);

Assignee:

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/08 (2006.01);
U.S. Cl.
CPC ...
H03K 5/08 (2013.01);
Abstract

Apparatus and methods for setting and clamping a node voltage are provided herein. In certain embodiments, a node control circuit includes a setting circuit for setting a voltage of a node based on a set signal. The node control circuit further includes at least one of a p-type follower clamp for clamping the node to an upper voltage limit based on an upper clamping control signal or an n-type follower clamp for clamping the node to a lower voltage limit based on a lower clamping control signal. When including both clamps, the node operates with a voltage level set by the set signal, but saturates at the upper voltage limit established by the upper clamping control signal and at the lower voltage limit established by the lower clamping control signal.


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