The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2020
Filed:
Apr. 29, 2019
Applicant:
4ds Memory, Limited, West Perth, AU;
Inventor:
Seshubabu Desu, Fremont, CA (US);
Assignee:
4DS MEMORY, LIMITED, Perth, Western Australia, unknown;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 45/00 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1233 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); H01L 45/08 (2013.01); H01L 45/1246 (2013.01); H01L 45/1266 (2013.01); H01L 45/147 (2013.01); H01L 45/16 (2013.01); H01L 45/1608 (2013.01); G11C 2013/009 (2013.01); G11C 2013/0045 (2013.01); G11C 2213/13 (2013.01); G11C 2213/31 (2013.01); G11C 2213/51 (2013.01); G11C 2213/52 (2013.01); G11C 2213/55 (2013.01);
Abstract
A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.