The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2020

Filed:

Mar. 20, 2018
Applicant:

Samsung Display Co., Ltd., Yongin-si, Gyeonggi-Do, KR;

Inventors:

Sun Ho Kim, Yongin-si, KR;

Ju Chan Park, Yongin-si, KR;

Young Gug Seol, Yongin-si, KR;

Sun Hee Lee, Yongin-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); H01L 51/50 (2006.01); H01L 51/56 (2006.01); G09G 3/3233 (2016.01);
U.S. Cl.
CPC ...
H01L 27/3276 (2013.01); H01L 27/3258 (2013.01); H01L 27/3265 (2013.01); H01L 51/5096 (2013.01); H01L 51/56 (2013.01); G09G 3/3233 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0262 (2013.01); H01L 27/3209 (2013.01); H01L 27/3262 (2013.01); H01L 27/3272 (2013.01); H01L 2227/323 (2013.01);
Abstract

A display device includes a substrate including a pixel region and a peripheral region. The display device also includes a plurality of pixels provided in the pixel region for displaying an image. The display device also includes a light emitting element provided in each pixel for emitting light. The display device includes a first transistor provided in each pixel for driving the light emitting element, and a second transistor connected to the first transistor. The display device includes an insulating layer disposed between a second semiconductor layer of the second transistor and the substrate; and a crack blocking layer disposed between the insulating layer and the second semiconductor layer of the second transistor. A first semiconductor layer of the first transistor and the second semiconductor layer of the second transistor are provided in layers different from each other.


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