The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2020

Filed:

Sep. 12, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Takashi Ando, Tuckahoe, NY (US);

Barry P. Linder, Hastings-on-Hudson, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/02178 (2013.01); H01L 21/28088 (2013.01); H01L 21/28185 (2013.01); H01L 21/28194 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 27/0211 (2013.01); H01L 27/092 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01);
Abstract

A complementary metal-oxide semiconductor (CMOS) circuit and a method of fabricating the device are described. The circuit includes an n-channel field effect transistor (nFET), the nFET including a high-k dielectric layer on an interlayer. The CMOS circuit also includes a p-channel field effect transistor (pFET), the pFET including the high-k dielectric layer on the interlayer and additionally including an aluminum-based cap layer between the high-k dielectric layer and a pFET work function setting metal. Metal atoms from the cap layer do not intermix with the interlayer.


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