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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10622231 B1

PDFFull Text
Date of Patent:
Apr. 14, 2020

Filed:

Sep. 25, 2018

Method of manufacturing semiconductor package

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jin-chan Ahn, Hwaseong-si, KR;

Won-young Kim, Seoul, KR;

Kyung-seon Hwang, Incheon, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Andres Munoz

Int. Cl.
CPC ...
H01L 21/67 (2006.01); G01R 31/00 (2006.01); H01L 21/66 (2006.01); G01R 31/317 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/544 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); G01R 31/28 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67271 (2013.01); G01R 31/00 (2013.01); G01R 31/31718 (2013.01); H01L 21/565 (2013.01); H01L 21/67282 (2013.01); H01L 21/78 (2013.01); H01L 22/14 (2013.01); H01L 22/20 (2013.01); H01L 23/544 (2013.01); H01L 24/97 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); G01R 31/2896 (2013.01); H01L 21/561 (2013.01); H01L 23/3128 (2013.01); H01L 24/16 (2013.01); H01L 2223/54433 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A method of manufacturing a semiconductor package includes obtaining a plurality of individual chips classified according to a test bin item as a result of performing an electrical die sorting (EDS) process including testing electrical characteristics of a plurality of chips at a wafer level, packaging the individual chips on corresponding chip mounting regions of a circuit substrate and forming a plurality of individual packages based on position information of the chip mounting regions, each of the individual packages having test bin item information corresponding to the test bin item, classifying the plurality of individual packages according to the test bin item based on the test bin item information, and testing the individual packages classified according to the test bin item.

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