The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2020

Filed:

Dec. 14, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Bipin Duggal, Irvine, CA (US);

Naishad Parikh, Bangalore, IN;

Ritu Chaba, San Diego, CA (US);

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 8/18 (2006.01); G11C 7/10 (2006.01); H03H 11/26 (2006.01); G11C 7/04 (2006.01); G11C 7/22 (2006.01); H03K 5/131 (2014.01); H03K 5/13 (2014.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G11C 7/04 (2013.01); G11C 7/1012 (2013.01); G11C 7/222 (2013.01); H03H 11/265 (2013.01); H03K 5/13 (2013.01); H03K 5/131 (2013.01);
Abstract

An apparatus including a memory subsystem. The memory subsystem includes a data input and a clock input. The apparatus also includes a variable delay circuit coupled to one of the data input or the clock input. Additionally, the apparatus includes a controller coupled to the variable delay circuit. The controller is configured to dynamically control the delay of the variable delay circuit. The controller may adjust the delay of the variable delay circuit based on at least one of timing data for a memory subsystem design of the memory subsystem, timing data for the memory subsystem, a voltage applied to the memory subsystem, or a temperature of the memory subsystem.


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