The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2020

Filed:

Feb. 20, 2018
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Chika Tanaka, Fujisawa, JP;

Keiji Ikeda, Kawasaki, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/06 (2006.01); G06N 3/063 (2006.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01); G11C 11/4096 (2006.01); H01L 29/786 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G06N 20/00 (2019.01); G11C 8/16 (2006.01); G11C 11/4091 (2006.01); G11C 11/405 (2006.01); G11C 11/56 (2006.01); G11C 11/44 (2006.01); G11C 11/54 (2006.01); G11C 11/4094 (2006.01); G06N 3/04 (2006.01); G06N 3/08 (2006.01);
U.S. Cl.
CPC ...
G06N 3/0635 (2013.01); G06N 3/063 (2013.01); G06N 20/00 (2019.01); G11C 8/16 (2013.01); G11C 11/405 (2013.01); G11C 11/4076 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); G11C 11/44 (2013.01); G11C 11/54 (2013.01); G11C 11/565 (2013.01); H01L 27/1225 (2013.01); H01L 27/1255 (2013.01); H01L 29/42384 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01); G06N 3/049 (2013.01); G06N 3/088 (2013.01); G11C 11/4094 (2013.01);
Abstract

According to an embodiment, a semiconductor device includes M write word lines, M read word lines, N write bit lines, N read bit lines, N source lines, and M×N cells. The M×N cells are arranged in a matrix including M rows×N columns. A cell in an m-th row×an n-th column includes a first FET, a second FET, and a capacitor. The first FET is connected to an m-th write word line at a gate, to an n-th write bit line at a drain, and to a source of the second FET at a source. The second FET is connected to an m-th read word line at a gate and to an n-th read bit line at a drain. The capacitor is connected to an n-th source line at one end and to the source of the first RET at the other end.


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