The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2020

Filed:

Nov. 02, 2017
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Kenneth D. Johnson, Seattle, WA (US);

Sai Ganesh Ramachandran, Redmond, WA (US);

Xin David Zhang, Redmond, WA (US);

Arun Upadhyaya Kishan, Kirkland, WA (US);

David Alan Hepkin, Redmond, WA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/55 (2013.01); G06F 12/1009 (2016.01); G06F 12/1045 (2016.01); G06F 12/14 (2006.01); G06F 9/455 (2018.01); G06F 21/62 (2013.01);
U.S. Cl.
CPC ...
G06F 21/556 (2013.01); G06F 9/45558 (2013.01); G06F 12/1009 (2013.01); G06F 12/1045 (2013.01); G06F 12/145 (2013.01); G06F 21/6281 (2013.01); G06F 2009/45579 (2013.01); G06F 2009/45583 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/152 (2013.01); G06F 2212/60 (2013.01); G06F 2212/657 (2013.01); G06F 2212/68 (2013.01); G06F 2221/034 (2013.01);
Abstract

Speculative side channels exist when memory is accessed by speculatively-executed processor instructions. Embodiments use uncacheable memory mappings to close speculative side channels that could allow an unprivileged execution context to access a privileged execution context's memory. Based on allocation of memory location(s) to the unprivileged execution context, embodiments map these memory location(s) as uncacheable within first page table(s) corresponding to the privileged execution context, but map those same memory locations as cacheable within second page table(s) corresponding to the unprivileged execution context. This prevents a processor from carrying out speculative execution of instruction(s) from the privileged execution context that access any of this memory allocated to the unprivileged execution context, due to the unprivileged execution context's memory being mapped as uncacheable for the privileged execution context. Performance for the unprivileged execution context is substantially unaffected, however, since this memory is mapped as cacheable for the unprivileged execution context.


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