The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2020
Filed:
Dec. 18, 2017
Applicant:
Nvidia Corp., Santa Clara, CA (US);
Inventors:
Michael Sullivan, San Jose, CA (US);
Siva Hari, Santa Clara, CA (US);
Brian Zimmer, Berkley, CA (US);
Timothy Tsai, Santa Clara, CA (US);
Stephen W Keckler, Austin, TX (US);
Assignee:
NVIDIA Corp., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G06F 11/10 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 11/22 (2006.01); G06F 11/16 (2006.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0727 (2013.01); G06F 9/3004 (2013.01); G06F 9/30018 (2013.01); G06F 9/30098 (2013.01); G06F 9/3832 (2013.01); G06F 9/3857 (2013.01); G06F 11/0793 (2013.01); G06F 11/104 (2013.01); G06F 11/1048 (2013.01); G06F 11/1497 (2013.01); G06F 11/1641 (2013.01); G06F 11/2236 (2013.01);
Abstract
A family of software-hardware cooperative mechanisms to accelerate intra-thread duplication leverage the register file error detection hardware to implicitly check the data from duplicate instructions, avoiding the overheads of instruction checking and enforcing low-latency error detection with strict error containment guarantees.