The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Mar. 16, 2015
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Mirko Dondini, Catania, IT;

Daniele Mangano, San Gregorio di Catania, IT;

Assignee:

STMICROELECTRONICS S.R.L., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 9/30 (2018.01); G06F 9/318 (2018.01); H04L 29/08 (2006.01); H04L 12/721 (2013.01); G06F 13/40 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
H04L 67/1097 (2013.01); G06F 13/1626 (2013.01); G06F 13/4022 (2013.01); H04L 45/72 (2013.01); G06F 13/4059 (2013.01); G06F 2213/0038 (2013.01);
Abstract

A system to manage out-of-order traffic in an interconnect network has initiators that provide requests through the interconnect network to memory resource targets and provide responses back through the interconnect network. The system includes components upstream the interconnect network to perform response re-ordering, which include memory to store responses from the interconnect network and a memory map controller to store the responses on a set of logical circular buffers. Each logical circular buffer corresponds to an initiator. The memory map controller computes an offset address for each buffer and stores an offset address of a given request received on a request path. The controller computes an absolute write memory address where responses are written in the memory, the response corresponding to the given request based on the given request offset address. The memory map controller also performs an order-controlled parallel read of the logical circular buffers and routes the data read from the memory to the corresponding initiator.


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