The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Apr. 11, 2017
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventor:

Alan Fiedler, Mountain View, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); H03K 5/135 (2006.01); H03L 7/081 (2006.01); H03L 7/089 (2006.01); H03L 7/093 (2006.01); H04L 7/033 (2006.01); G06F 1/06 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0812 (2013.01); G06F 1/06 (2013.01); H03K 5/135 (2013.01); H03L 7/0895 (2013.01); H03L 7/093 (2013.01);
Abstract

The control signal edges of pull-up and pull-down output transistors are aligned by a feedback system. The feedback system works to align the edges of these pull-up and pull-down control pulses while also reducing and/or minimizing any overlap of pull-up and pull-down control pulses. The feedback system uses a proportional feedback loop and an integral feedback loop. The proportional feedback loop controls the crossover voltages of the differential clock signals used to generate the pull-up and pull-down pulses. The integral feedback loop controls the crossover voltages of the differential clock signals output by the delay elements of a delay-locked loop. These crossover voltages are controlled by the feedback loops such that the edges of the pull-down control pulses are aligned to the edges of the pull-up control pulses (and vice versa) without creating excessive overlap.


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