The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2020
Filed:
Aug. 01, 2019
SK Hynix Inc., Icheon, KR;
Industry-academic Cooperation Foundation, Yonsei University, Seoul, KR;
Kangwook Jo, Goyang, KR;
Jeongbin Kim, Seoul, KR;
Minyoung Im, Seoul, KR;
Taehee You, Incheon, KR;
Eui-Young Chung, Seongnam, KR;
Hongil Yoon, Seoul, KR;
SK hynix Inc., Icheon, KR;
INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY, Seoul, KR;
Abstract
A technology mapping method for a FPGA includes converting a gate level netlist into an AND-Inverter Graph (AIG) netlist, selecting a node among nodes included in the AIG netlist, generating a cut set including one or more cuts corresponding to the selected node, selecting a best cut by sorting the cuts included in the cut set according to predetermined criteria and outputting a LUT netlist including the best cut, wherein the predetermined criteria include a maximum difference of levels of sub-cuts connected in each cut as a first criterion.