The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Dec. 26, 2017
Applicant:

Trumpf Huettinger Gmbh + Co. KG, Freiburg, DE;

Inventors:

Andre Grede, Freiburg, DE;

Alexander Alt, Freiburg, DE;

Daniel Gruner, Muellheim, DE;

Anton Labanc, Ehrenkirchen, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 1/52 (2006.01); H01J 37/32 (2006.01); H03F 3/30 (2006.01); H03F 3/193 (2006.01); H03F 3/217 (2006.01); H01L 23/66 (2006.01); H01L 27/06 (2006.01); H01L 29/78 (2006.01); H03F 3/195 (2006.01);
U.S. Cl.
CPC ...
H03F 1/523 (2013.01); H01J 37/32174 (2013.01); H01L 23/66 (2013.01); H01L 27/0629 (2013.01); H01L 29/7816 (2013.01); H03F 3/193 (2013.01); H03F 3/195 (2013.01); H03F 3/2176 (2013.01); H03F 3/3001 (2013.01); H01L 2223/6616 (2013.01); H03F 2200/451 (2013.01);
Abstract

A non-linear high-frequency amplifier arrangement suitable for generating power outputs ≥1 kW at frequencies of ≥1 MHz for plasma excitation is provided. The arrangement includes two LDMOS transistors each connected by their source connection to aground connection point, where the LDMOS transistors have the same design and are arranged in an assembly, a power transformer whose primary winding is connected to drain connections of the LDMOS transistors, a signal transformer whose secondary winding is connected by a first end to a gate connection of one LDMOS transistor and by a second end to a gate connection of the other LDMOS transistor, and a feedback path from the drain connection to the gate connection of each of the LDMOS transistors.


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