The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Nov. 11, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Dongmin Park, San Diego, CA (US);

Jong Min Park, San Diego, CA (US);

Lai Kan Leung, San Marcos, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 19/22 (2006.01); H02M 7/217 (2006.01); G06K 19/07 (2006.01);
U.S. Cl.
CPC ...
H02M 7/217 (2013.01); G06K 19/0707 (2013.01); G06K 19/0715 (2013.01); G06K 19/0723 (2013.01);
Abstract

A method and system for self-powering a clock input buffer is disclosed. The system includes an input node adapted to receive an alternating current (AC) signal having an instantaneous voltage oscillating between a minimum voltage and a maximum voltage. The system includes a pass transistor having a voltage controlled terminal, a first transfer terminal, and a second transfer terminal. The first transfer terminal connects to the input node and the second transfer terminal connects to a power node. The circuit also includes a plurality of transistors adapted to form a logic gate connected to the power node, and having a sensing terminal connected to the input node and an output terminal connected to the voltage controlled terminal. The logic gate produces a control voltage on the output terminal in response to an input voltage on the sensing terminal. The circuit also includes an energy-storage element having a first terminal connected to the power node.


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