The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2020
Filed:
Apr. 06, 2018
Sony Corporation, Tokyo, JP;
Taku Umebayashi, Kanagawa, JP;
Shunichi Sukegawa, Kanagawa, JP;
Takashi Yokoyama, Kanagawa, JP;
Masanori Hosomi, Tokyo, JP;
Yutaka Higo, Kanagawa, JP;
SONY CORPORATION, Tokyo, JP;
Abstract
The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat. A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.