The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Jul. 27, 2018
Applicant:

Silicon Space Technology Corporation, Austin, TX (US);

Inventor:

Steven Howard Voldman, Lake Placid, NY (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 27/12 (2006.01); H01L 23/556 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1083 (2013.01); H01L 23/556 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/0646 (2013.01); H01L 29/1087 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01);
Abstract

A low electrical and thermal resistance FinFET device includes a semiconductor body, a fin body on the substrate wafer, an isolation structure forming a fin connecting region, a gate dielectric on the fin body extending above the isolation structure, a FinFET gate electrode on the gate dielectric, a heavily-doped buried layer in the semiconductor body extending under said fin, and a vertical conductive region extending from the semiconductor body surface to the heavily-doped buried layer. Additionally, a fin body-to-buried layer implanted region disposed in the fin connecting region provides a low electrical and thermal resistance shunt from the fin body to the heavily-doped buried layer.


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