The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

May. 20, 2019
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Junji Hirase, Osaka, JP;

Yoshinori Takami, Toyama, JP;

Yoshihiro Sato, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 27/30 (2006.01); H04N 5/369 (2011.01); H04N 5/359 (2011.01);
U.S. Cl.
CPC ...
H01L 27/14603 (2013.01); H01L 27/14609 (2013.01); H01L 27/307 (2013.01); H04N 5/379 (2018.08); H04N 5/359 (2013.01);
Abstract

An imaging device according to the present disclosure includes: a photoelectric converter that generates signal charge; a semiconductor substrate including a first semiconductor layer containing an impurity of a first conductivity type and an impurity of a second conductivity type; and a first transistor including a first impurity region of the second conductivity type in the first semiconductor layer. The first semiconductor layer includes: a charge accumulation region of the second conductivity type, for accumulating the signal charge; and a blocking structure between the charge accumulation region and the first transistor. The blocking structure includes a second impurity region of the first conductivity type, a third impurity region of the second conductivity type, and a fourth impurity region of the first conductivity type, which are arranged in that order in a direction from the first impurity region toward the charge accumulation region, at the surface of the first semiconductor layer.


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