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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10615192 B1

PDFFull Text
Date of Patent:
Apr. 07, 2020

Filed:

Jul. 09, 2018

Array substrate assembly, method of manufacturing array substrate assembly, display panel and display apparatus

Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Hefei Xinsheng Optoelectronics Technology Co., Ltd., Hefei, Anhui, CN;

Inventors:

Yuankui Ding, Beijing, CN;

Guangcai Yuan, Beijing, CN;

Ce Zhao, Beijing, CN;

Bin Zhou, Beijing, CN;

Jun Cheng, Beijing, CN;

Zhaofan Liu, Beijing, CN;

Yingbin Hu, Beijing, CN;

Yongchao Huang, Beijing, CN;

Assignees:

BOE TECHNOLOGY GROUP CO, LTD., Beijing, CN;

HEFEI, XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., Hefei, Anhui, CN;

Attorney:

Kinney & Lange, P.A.

Primary Examiner:

Karen Kusumakar

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 21/027 (2006.01); G03F 7/038 (2006.01); G03F 7/20 (2006.01); G03F 7/26 (2006.01); G03F 7/42 (2006.01); G03F 7/16 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/127 (2013.01); G03F 7/038 (2013.01); G03F 7/16 (2013.01); G03F 7/2002 (2013.01); G03F 7/2037 (2013.01); G03F 7/26 (2013.01); G03F 7/422 (2013.01); H01L 21/0274 (2013.01); H01L 27/1225 (2013.01); H01L 27/1262 (2013.01); H01L 27/1288 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01);
Abstract

A method of manufacturing an array substrate assembly, an array substrate assembly manufactured by the method, and a display panel including the array substrate assembly are disclosed. The method includes: providing a substrate, the substrate having a first region as a preset semiconductor-removed region, and a second region as a remaining region; forming, in the first region of the substrate, a semiconductor removing layer corrodible by a corrosive solution; and forming a semiconductor layer on the substrate formed with the semiconductor removing layer, so that the semiconductor layer covers the semiconductor removing layer.

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