The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Nov. 22, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

David J. Frank, Yorktown Heights, NY (US);

Paul M. Solomon, Yorktown Heights, NY (US);

Xiao Sun, Yorktown Heights, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/1159 (2017.01); H01L 27/092 (2006.01); H01L 29/45 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); G11C 11/22 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1159 (2013.01); G11C 11/221 (2013.01); G11C 11/223 (2013.01); H01L 21/823857 (2013.01); H01L 27/092 (2013.01); H01L 27/11 (2013.01); H01L 29/40111 (2019.08); H01L 29/45 (2013.01); H01L 29/78391 (2014.09); H01L 21/823807 (2013.01);
Abstract

A field-effect transistor includes a semiconductor substrate having first, second, third, and fourth sides, and a ferroelectric gate stack on an upper surface of the substrate. The ferroelectric gate stack includes a gate insulating layer; and a ferroelectric material layer on the gate insulating layer. Portions of the upper surface of the substrate between the first side and the ferroelectric gate stack and between the second side and the ferroelectric gate stack are doped with n-type impurities, and portions of the upper surface of the substrate between the third side and the ferroelectric gate stack and between the fourth side and the ferroelectric gate stack are doped with p-type impurities. A presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.


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