The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Dec. 05, 2018
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Dong Ho Kang, Icheon-si, KR;

Jin Wook Kim, Yongin-si, KR;

Yang Uk Son, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/4094 (2006.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 7/109 (2013.01); G11C 7/1063 (2013.01); G11C 7/222 (2013.01); G11C 11/4087 (2013.01); G11C 11/4093 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01);
Abstract

A semiconductor device includes a delay circuit and a column signal generation circuit. The delay circuit delays a write signal by a sum of a write latency time and a burst operation time to generate a write pulse, delays a read signal to generate a read pulse, and generates a pre-charge signal which is enabled after a predetermined period elapses from a time when the write signal is generated. The column signal generation circuit generates a column signal from a chip selection signal and a command/address signal when the write pulse or the read pulse is inputted to the column signal generation circuit. The column signal is a signal for selecting at least one memory cell included in one of a plurality of banks.


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