The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Jul. 27, 2017
Applicant:

Arizona Board of Regents on Behalf of Arizona State University, Scottsdale, AZ (US);

Inventors:

Jae-sun Seo, Tempe, AZ (US);

Deepak Kadetotad, Tempe, AZ (US);

Sairam Arunachalam, Tempe, AZ (US);

Chaitali Chakrabarti, Tempe, AZ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G10L 15/16 (2006.01); G06N 3/063 (2006.01); G10L 15/22 (2006.01); G06K 9/62 (2006.01); G06N 3/04 (2006.01); G10L 15/28 (2013.01);
U.S. Cl.
CPC ...
G10L 15/16 (2013.01); G06K 9/6267 (2013.01); G06N 3/0472 (2013.01); G06N 3/063 (2013.01); G10L 15/22 (2013.01); G10L 15/285 (2013.01); G10L 2015/223 (2013.01);
Abstract

Aspects disclosed in the detailed description include memory compression in a deep neural network (DNN). To support a DNN application, a fully connected weight matrix associated with a hidden layer(s) of the DNN is divided into a plurality of weight blocks to generate a weight block matrix with a first number of rows and a second number of columns. A selected number of weight blocks are randomly designated as active weight blocks in each of the first number of rows and updated exclusively during DNN training. The weight block matrix is compressed to generate a sparsified weight block matrix including exclusively active weight blocks. The second number of columns is compressed to reduce memory footprint and computation power, while the first number of rows is retained to maintain accuracy of the DNN, thus providing the DNN in an efficient hardware implementation without sacrificing accuracy of the DNN application.


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