The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Dec. 21, 2018
Applicant:

Seiko Epson Corporation, Tokyo, JP;

Inventors:

Mitsutoshi Miyasaka, Suwa, JP;

Yoichi Momose, Matsumoto, JP;

Kiyoshi Sekijima, Shiojiri, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/30 (2006.01); G09G 3/3233 (2016.01); G09G 3/20 (2006.01); G09G 3/3258 (2016.01); G02B 27/01 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); G02B 27/01 (2013.01); G09G 3/2007 (2013.01); G09G 3/3258 (2013.01); G09G 2300/0842 (2013.01); G09G 2320/0233 (2013.01); H01L 27/3276 (2013.01);
Abstract

An electro-optical device includes a first scan line, a data line, and a pixel circuit provided at a position corresponding to intersections of the first scan line and the data line. The pixel circuit includes a light emitting element, a memory circuit, a first transistor, and a second transistor. The first transistor is electrically connected in series to the light emitting element, and a gate of the first transistor is electrically connected to the memory circuit. The second transistor is disposed between the data line and an input of a first inverter. The third transistor is disposed between an output terminal of a second inverter and the input of the first inverter. When the second transistor turns from an OFF-state to an ON-state, the third transistor is not in an ON-state.


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