The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2020
Filed:
May. 29, 2018
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Henri Fraisse, Sunnyvale, CA (US);
Dinesh D. Gaitonde, Fremont, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5077 (2013.01); G06F 17/504 (2013.01); G06F 17/5054 (2013.01); G06F 17/5068 (2013.01); G06F 17/5072 (2013.01); G06F 17/5081 (2013.01); G06F 2217/08 (2013.01);
Abstract
Method and system relate generally to generating a physical design for a circuit design. In such a method, a logical network is obtained from a logical netlist for the circuit design. A physical network for an integrated circuit chip is obtained. The physical network is converted into a routing graph. The logical network and the routing graph are combined to build an extended network. Routing is performed on the extended network for the logical netlist to perform placement and the routing concurrently to provide the physical design.