The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2020
Filed:
May. 17, 2018
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Manish Srivastava, Bangalore, IN;
Esakkimuthu Dhakshinamoorthy, Bangalore, IN;
Neha Gupta, Bangalore, IN;
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/501 (2006.01); G06F 7/503 (2006.01); H02M 1/088 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
G06F 7/503 (2013.01); G06F 7/5016 (2013.01); H02M 1/088 (2013.01); H03K 19/212 (2013.01);
Abstract
A full adder is provided in which a sum logic circuit for producing the sum signal and a carry-out logic circuit for producing the carry-out output paths do not share internal nodes. In addition, the sum logic circuit and the carry-out logic circuit are both configured to obviate the need for transmission gates with respect to forming the sum signal and the carry-out signal.