The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Jan. 05, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Michael Brunolli, Escondido, CA (US);

Stephen Thilenius, San Diego, CA (US);

Patrick Isakanian, El Dorado Hills, CA (US);

Vaishnav Srinivas, Oceanside, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01); G06F 1/3234 (2019.01); G11C 7/10 (2006.01); G11C 11/4074 (2006.01); G06F 1/3287 (2019.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 1/32 (2019.01); H04L 25/02 (2006.01); G06F 1/3209 (2019.01); G06F 1/3296 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3275 (2013.01); G06F 1/32 (2013.01); G06F 1/3209 (2013.01); G06F 1/3287 (2013.01); G06F 1/3296 (2013.01); G06F 13/16 (2013.01); G06F 13/4086 (2013.01); G06F 13/4243 (2013.01); G11C 7/1072 (2013.01); G11C 11/4074 (2013.01); H04L 25/0264 (2013.01); H04L 25/0278 (2013.01); Y02D 10/14 (2018.01); Y02D 10/172 (2018.01); Y02D 50/20 (2018.01);
Abstract

A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.


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