The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Apr. 12, 2018
Applicant:

Analog Devices Global Unlimited Company, Hamilton, BM;

Inventors:

Hanqing Wang, Beijing, CN;

Gerard Mora-Puchalt, Catarroja, ES;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/16 (2006.01); G05F 3/16 (2006.01); H03K 17/687 (2006.01); H03F 3/45 (2006.01); H03F 3/00 (2006.01);
U.S. Cl.
CPC ...
G05F 3/16 (2013.01); H03F 3/005 (2013.01); H03F 3/45475 (2013.01); H03K 17/687 (2013.01); H03F 2200/129 (2013.01); H03F 2203/45512 (2013.01); H03F 2203/45551 (2013.01);
Abstract

A common mode reference circuit comprises a divider stage and an output stage. The divider stage includes a first n-channel field effect transistor and p-channel filed effect transistor (NFET/PFET) pair connected in series to a high supply voltage circuit node; and a second NFET/PFET pair connected in series to a low supply voltage circuit node. The output stage includes a first FET connected as a current mirror to a transistor of the first NFET/PFET pair; a second FET connected as a current mirror to a transistor of the second NFET/PFET pair; and a common mode reference output at a series connection from the first FET to the second FET.


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