The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2020
Filed:
Nov. 04, 2016
Sino Ic Technology Co., Ltd., Pudong New Area, CN;
Bin Luo, Pudong New Area, CN;
Hua Wang, Pudong New Area, CN;
Shouyin Ye, Pudong New Area, CN;
Xuefei Tang, Pudong New Area, CN;
Jianbo Ling, Pudong New Area, CN;
Jianming Ye, Pudong New Area, CN;
SINO IC TECHNOLOGY CO., LTD., Pudong New Area, CN;
Abstract
A configuration and testing method and system for an FPGA chip using a bumping process are disclosed, the method includes creating configuration files for an FPGA chip under test and storing them in a memory; reading, by a master FPGA, a configuration code stream of corresponding configuration codes from the mass memory, configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful; if the configuration is successful, converting the configuration code stream into a test signal source file that is recognizable, executable and reusable by multiple pieces of test equipment by a developed algorithm and a conversion tool; and automatically loading the test signal source file onto the FPGA chip under test in real time by advanced test equipment.