The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Mar. 09, 2018
Applicant:

Mediatek Inc., Hsinchu, TW;

Inventors:

Chong-You Lee, Hsinchu, TW;

Timothy Perrin Fisher-Jeffes, San Jose, CA (US);

Maoching Chiu, Hsinchu, TW;

Wei Jen Chen, Hsinchu, TW;

Cheng-Yi Hsu, Hsinchu, TW;

Ju-Ya Chen, Hsinchu, TW;

Yen Shuo Chang, Hsinchu, TW;

Assignee:

MEDIATEK INC., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/11 (2006.01); H03M 13/15 (2006.01); H03M 13/25 (2006.01);
U.S. Cl.
CPC ...
H03M 13/116 (2013.01); H03M 13/118 (2013.01); H03M 13/15 (2013.01); H03M 13/616 (2013.01); H03M 13/618 (2013.01); H03M 13/6306 (2013.01); H03M 13/6516 (2013.01); H03M 13/255 (2013.01);
Abstract

Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits. The processing circuitry is also configured to decode a received codeword having a received data unit based on the matrix and to obtain a decoded data unit.


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