The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2020
Filed:
Sep. 20, 2018
Electronics and Telecommunications Research Institute, Daejeon, KR;
Hokyun Ahn, Daejeon, KR;
Min Jeong Shin, Daejeon, KR;
Jeong Jin Kim, Jeonju-si, KR;
Hae Cheon Kim, Daejeon, KR;
Jae Won Do, Daejeon, KR;
Byoung-Gue Min, Sejong-si, KR;
Hyung Sup Yoon, Daejeon, KR;
Hyung Seok Lee, Daejeon, KR;
Jong-Won Lim, Daejeon, KR;
Sungjae Chang, Daejeon, KR;
Hyunwook Jung, Daejeon, KR;
Kyu Jun Cho, Daejeon, KR;
Dong Min Kang, Daejeon, KR;
Dong-Young Kim, Daejeon, KR;
Seong-Il Kim, Daejeon, KR;
Sang-Heung Lee, Daejeon, KR;
Jongmin Lee, Daejeon, KR;
Hong Gu Ji, Daejeon, KR;
Electronics and Telecommunications Research Institute, Daejeon, KR;
Abstract
Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.