The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Jul. 01, 2016
Applicant:

Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, CN;

Inventors:

Xinhong Cheng, Shanghai, CN;

Xinchang Li, Shanghai, CN;

Zhonghao Wu, Shanghai, CN;

Dawei Xu, Shanghai, CN;

Yuehui Yu, Shanghai, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 27/12 (2006.01); H01M 10/42 (2006.01); H01L 29/78 (2006.01); H01L 21/761 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H03K 17/567 (2006.01); H03K 17/687 (2006.01); H03K 17/693 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/761 (2013.01); H01L 21/76283 (2013.01); H01L 29/0653 (2013.01); H01L 29/78 (2013.01); H01M 10/42 (2013.01); H01M 10/4257 (2013.01); H01M 10/4264 (2013.01); H03K 17/567 (2013.01); H03K 17/6872 (2013.01); H03K 17/693 (2013.01); H01L 27/092 (2013.01); H01M 2010/4271 (2013.01); H01M 2220/20 (2013.01);
Abstract

A battery management chip circuit on the basis of an SOI process. The battery management chip circuit comprises a high-voltage multiplexer MUX, a voltage reference circuit, a Sigma-delta ADC (comprising an analog modulator and a digital filter), an SPI communication circuit, a function control circuit and a voltage value register. The battery management chip circuit is integrated on the basis of an SOI high-voltage process, and particularly, high-voltage MOS transistors adopted by the battery management chip circuit are high-voltage MOS device units on the basis of the SOI process. In addition, the present invention highlights the design of interface circuit-chopper circuit of the high-voltage multiplexer MUX and the Sigma-delta ADC, so as to describe the advantages such as decrease of difficulty of circuit design and reduction of layout area brought about when the present invention adopts the SOI process design and tape-out.


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