The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Jun. 18, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Yang Xiu, Urbana, IL (US);

Aravind C. Appaswamy, Plano, TX (US);

Akram Salman, Plano, TX (US);

Mariano Dissegna, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 29/73 (2006.01); H01L 29/417 (2006.01); H01L 29/732 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0259 (2013.01); H01L 29/0623 (2013.01); H01L 29/0646 (2013.01); H01L 29/41708 (2013.01); H01L 29/7322 (2013.01);
Abstract

According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.


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