The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Feb. 12, 2018
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Satoru Akiyama, Tokyo, JP;

Hiroyoshi Kobayashi, Tokyo, JP;

Hisao Inomata, Tokyo, JP;

Sei Saitou, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 23/495 (2006.01); H01L 21/82 (2006.01); H03F 1/22 (2006.01); H01L 23/498 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 29/78 (2006.01); H01L 29/808 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 21/8213 (2013.01); H01L 23/4952 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 23/49844 (2013.01); H01L 29/1608 (2013.01); H01L 29/2003 (2013.01); H01L 29/78 (2013.01); H01L 29/808 (2013.01); H03F 1/223 (2013.01); H03F 1/226 (2013.01); H01L 23/3107 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48472 (2013.01); H01L 2224/49113 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor device, including a first semiconductor chip including a first substrate having a semiconductor larger in bandgap than silicon, the first semiconductor chip being formed with a first FET including a first gate electrode, a first source, and a first drain, a second semiconductor chip including a second substrate having a semiconductor larger in bandgap than silicon, the second semiconductor chip being formed with a second FET having a second gate electrode, a second source, and a second drain, and a third semiconductor chip including a third substrate having silicon, the third semiconductor chip being formed with a MOSFET including a third gate electrode, a third source, and a third drain. The first semiconductor chip and the second semiconductor chip are mounted over a first chip mounting section, and the third semiconductor chip is mounted over a second chip mounting section.


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