The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Aug. 07, 2018
Applicant:

Taiyo Yuden Co., Ltd., Tokyo, JP;

Inventors:

Yuichi Sugiyama, Tokyo, JP;

Masashi Miyazaki, Tokyo, JP;

Yoshiki Hamada, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 23/13 (2006.01); H01L 21/48 (2006.01); H01L 25/16 (2006.01); H01L 23/34 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 23/13 (2013.01); H01L 23/3121 (2013.01); H01L 23/3142 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 25/16 (2013.01); H01L 23/34 (2013.01); H01L 2224/18 (2013.01);
Abstract

A semiconductor module includes a metal core layer that includes: a first metal layer and a second metal layer on the first metal layer, wherein a portion of the second metal layer is removed to expose a surface of the first metal layer, the removed portion of the second metal layer defining a cavity in the metal core layer having the exposed surface of the first metal layer as a bottom surface, and at least one of a side wall and the bottom surface of the cavity has a smoother surface profile than a surface of the first metal layer that is not exposed by the cavity and under the second metal layer; and a semiconductor element provided in the cavity, affixed to the bottom surface of the cavity with a fixing material containing a resin component.


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