The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Feb. 28, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Shinya Watanabe, Yokkaichi Mie, JP;

Keisuke Taira, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/306 (2006.01); H01L 23/544 (2006.01); H01L 21/311 (2006.01); H01L 27/11582 (2017.01); H01L 21/033 (2006.01); H01L 27/11575 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 27/11556 (2017.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/30608 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01); H01L 23/544 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01); B81C 2203/051 (2013.01); H01L 22/34 (2013.01); H01L 27/11556 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/54426 (2013.01);
Abstract

According to one embodiment, there is provided a method of manufacturing a semiconductor device which includes forming an alignment mark in a planned cutting line region of a first surface of a semiconductor substrate, forming a stacked structure above the first surface of the semiconductor substrate, removing the portion of the stacked structure present above the alignment mark, aligning the substrate in the lithography process, by causing infrared light to pass through the semiconductor substrate from a second surface thereof which is on a side opposite to the first surface thereof and performing positional alignment for exposure of a resist pattern based on the location of the alignment mark using infrared light reflected from the alignment mark, and exposing the resist, opening a pattern in the exposed resist, and further processing the semiconductor substrate using the resist pattern.


Find Patent Forward Citations

Watanabe, Shinya. (2020). Method of manufacturing a semiconductor device, and a semiconductor substrate (U.S. Patent No. 10607843). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10607843

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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