The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Sep. 05, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventor:

Yusuke Higashi, Zushi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 16/32 (2006.01); G11C 7/08 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 16/24 (2006.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G11C 7/08 (2013.01); G11C 11/223 (2013.01); G11C 11/2257 (2013.01); G11C 11/2275 (2013.01); G11C 11/2277 (2013.01); G11C 11/2293 (2013.01); G11C 11/5628 (2013.01); G11C 11/5657 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 16/34 (2013.01); G11C 16/3459 (2013.01); G11C 2029/0411 (2013.01);
Abstract

According to one embodiment, a semiconductor storage device includes: a first select transistor connected at a first end of a memory string; a second select transistor connected at a second end of the memory string; and a controller. In a write operation of writing data into a first memory cell transistor of the memory string, the controller performs: a first operation of applying a first voltage to a gate of the first memory cell transistor, while turning on the first and second select transistor; and a second operation of applying a second voltage higher than the first voltage to the gate of the first memory cell transistor, while turning off the first and second select transistor; and the second operation is performed after the first operation.


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