The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

May. 21, 2018
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Youngjae Jin, Seoul, KR;

Joonwoo Kim, Seoul, KR;

Youngook Song, Seoul, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G11C 11/406 (2006.01); G06F 11/00 (2006.01); G11C 11/408 (2006.01); G06F 13/16 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40615 (2013.01); G06F 11/004 (2013.01); G06F 11/106 (2013.01); G06F 13/16 (2013.01); G11C 11/4087 (2013.01); G11C 11/40611 (2013.01); G11C 11/40618 (2013.01); G11C 2211/4062 (2013.01);
Abstract

In an embodiment a semiconductor device may include a weakness detector configured to manage error occurrence information by dividing the memory device into a plurality of areas, to control a first refresh period for a first refresh request at each of the plurality of areas based on the error occurrence information and to generate a second refresh request for a second refresh address included in each of the plurality of areas based on the error occurrence information, and a refresh controller configured to generate a first refresh command according to the first refresh period and output the first refresh command to the memory device and to output a second refresh command and the second refresh address to the memory device according to the second refresh request and the second refresh address.


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