The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Mar. 01, 2018
Applicant:

Ribbon Communications Operating Company, Inc., Westford, MA (US);

Inventors:

Biswanath Dutta, Bengaluru, IN;

Shivakumar Venkataraman, Bengaluru, IN;

Christ John Kumar, Bengaluru, IN;

Pradheep Selvaraj, Bengaluru, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06T 1/60 (2006.01); G06T 1/20 (2006.01); G10L 19/16 (2013.01); G10L 19/008 (2013.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G10L 19/173 (2013.01); G06F 15/7839 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G10L 19/008 (2013.01);
Abstract

Context values used by filters corresponding to different streams are stored in an interleaved manner in a block of contiguous memory locations, e.g., of a buffer, to facilitate coalesced access of data units, e.g., context values, corresponding to different channels to facilitate filtering of multiple streams, e.g., audio streams, in parallel using a graphics processing unit. Context values corresponding to different channels are intentionally grouped together on an interleaved per channel basis in staging memory. This allows context values for multiple different streams to be transferred, e.g., loaded, as a single block e.g., with a context value of each different channel being loaded into a different GPU core. By organizing the context values to facilitate GPU processing, device operation is improved and execution efficiency is achieved as compared to what would be the case if multiple non-contiguous memory locations had to be implemented to load the cores of the GPU.


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