The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

May. 17, 2018
Applicant:

Lapis Semiconductor Co., Ltd., Yokohama, JP;

Inventors:

Hiroshi Tsuchi, Yokohama, JP;

Kenichi Shiibayashi, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3688 (2013.01); G09G 3/3614 (2013.01); G09G 3/3685 (2013.01); G09G 2310/0291 (2013.01); G09G 2320/0252 (2013.01); G09G 2330/021 (2013.01);
Abstract

A semiconductor device for driving a load of an object includes a differential circuit receiving an input signal and outputting differential output signals, first to fourth output circuits receiving the differential output signals, and a control circuit configured to respectively connect or disconnect the differential circuit to each of the first to fourth output circuits. The first output circuit is connected between high-level and mid-level power supply terminals and outputs a first output signal to the differential circuit, the second output circuit is connected between the high-level and mid-level power supply terminals, and outputs a second output signal to the load, a third output circuit is connected between mid-level and low-level power supply terminals, and outputs a third output signal to the differential circuit, and a fourth output circuit is connected between the mid-level low-level power supply terminals, and outputs a fourth output signal to the load.


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