The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Dec. 18, 2018
Applicant:

Seiko Epson Corporation, Tokyo, JP;

Inventors:

Mitsutoshi Miyasaka, Suwa, JP;

Yoichi Momose, Matsumoto, JP;

Kiyoshi Sekijima, Shiojiri, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/30 (2006.01); G09G 3/3225 (2016.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3225 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 2300/0842 (2013.01); G09G 2320/0233 (2013.01); G09G 2330/021 (2013.01);
Abstract

An electro-optical device includes a pixel circuit located at a position corresponding to an intersection of a scan line and a data line, a low potential line, and a high potential line. The pixel circuit includes a light emitting element, a first transistor, a memory circuit including a first inverter, a second inverter, and a second transistor, and a third transistor. The first transistor is disposed between an input of the first inverter and the data line. The second transistor is disposed between an output of the second inverter and the input. The third transistor and the light emitting element are disposed between the low potential line and the memory circuit. When the first transistor is in an ON-state, the second transistor and the third transistor are in an OFF-state.


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