The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Dec. 13, 2018
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Kejian You, Shenzhen, CN;

Weibo Xiong, Nanjing, CN;

Chao Kong, Nanjing, CN;

Binbin Wu, Nanjing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/78 (2006.01); G06F 3/023 (2006.01); G06F 9/32 (2018.01); G06F 12/06 (2006.01); H04L 12/741 (2013.01);
U.S. Cl.
CPC ...
G06F 15/7867 (2013.01); G06F 3/023 (2013.01); G06F 9/321 (2013.01); G06F 12/0646 (2013.01); H04L 45/54 (2013.01); H04L 45/745 (2013.01);
Abstract

A method for configuring an address table in a field-programmable gate array (FPGA), an FPGA, and a network device applying the FPGA, where the FPGA includes k storage blocks, the k is greater than or equal to the two, and the FPGA is configured to obtain a key, where the key is generated based on a first packet of a data stream, and a length of the key is equal to a key bit width of the FPGA, obtain an index number corresponding to the key, where the index number is used to search for a forwarding entry of the data stream, divide the key into k sub-keys, where each of the k sub-keys corresponds to one of the k storage blocks, determine an address entry of each of the k sub-keys in a corresponding storage block, and write a storage address to the address entry based on the index number.


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