The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Jan. 22, 2018
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Sanjay Trivedi, Bangalore, IN;

Ramesh Babu, Bangalore, IN;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 21/52 (2013.01); G06F 9/44 (2018.01); G06F 9/48 (2006.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 12/1483 (2013.01); G06F 9/30 (2013.01); G06F 9/4818 (2013.01); G06F 12/145 (2013.01); G06F 9/30134 (2013.01); G06F 9/30163 (2013.01); G06F 21/52 (2013.01); G06F 2212/1052 (2013.01);
Abstract

Methods, circuitries, and systems for real-time protection of a stack are provided. A stack protection circuitry includes interface circuitry and computation circuitry. The interface is circuitry configured to receive a return instruction from a central processing unit (CPU). The computation circuitry is configured to, in response to the return instruction, generate protection data that i) identifies a new topmost return address location that is below a current protected topmost return address location and ii) specifies read only access for the new topmost return address location. The interface circuitry is configured to provide the protection data to a memory protection unit to cause the memory protection unit to enforce a read only access restriction on the new topmost return address location.


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