The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

May. 26, 2017
Applicants:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Ati Technologies Ulc, Markham, CA;

Inventors:

Yunpeng Zhu, Shanghai, CN;

Jimshed Mirza, Toronto, CA;

Assignees:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

ATI Technologies ULC, Markham, CA;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06T 1/60 (2006.01); G06T 15/00 (2011.01); G06F 12/0811 (2016.01); G06F 9/30 (2018.01); G06F 12/084 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0223 (2013.01); G06F 9/3004 (2013.01); G06F 9/3824 (2013.01); G06F 9/3851 (2013.01); G06F 9/3887 (2013.01); G06F 9/4881 (2013.01); G06F 12/084 (2013.01); G06F 12/0811 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01); G06F 12/0207 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/455 (2013.01);
Abstract

Systems, apparatuses, and methods for generating flexibly addressed memory requests are disclosed. In one embodiment, a system includes a processor, control unit, and memory subsystem. The processor launches a plurality of threads on a plurality of compute units, wherein each thread generates memory requests without specifying target memory addresses. The threads executing on the plurality of compute units convey a plurality of memory requests to the control unit. The control unit generates target memory addresses for the plurality of received memory requests. In one embodiment, the memory requests are write requests, and the control unit interleaves write requests from the plurality of threads into a single output buffer stored in the memory subsystem. The control unit can be located in a cache, in a memory controller, or in another location within the system.


Find Patent Forward Citations

Loading…