The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Dec. 18, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Pankaj Bongale, Belgaum, IN;

Partha Ghosh, West Bengal, IN;

Rubin Ajit Parekhji, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/263 (2006.01); G06F 11/24 (2006.01); G01R 31/28 (2006.01); G06F 11/22 (2006.01); G06F 11/273 (2006.01);
U.S. Cl.
CPC ...
G06F 11/263 (2013.01); G01R 31/2822 (2013.01); G06F 11/2268 (2013.01); G06F 11/24 (2013.01); G06F 11/273 (2013.01);
Abstract

A test circuit that includes a circuit to be calibrated, an error generation circuit, and a simplex circuit coupled to one another. The circuit to be calibrated is configured to implement a first plurality of trim codes as calibration parameters for a corresponding plurality of components of the circuit to be calibrated and generate a first actual output. The error generation circuit is configured to generate a first error signal based on a difference between the first actual output and an expected output of the circuit to be calibrated. The simplex circuit is configured to receive the first error signal from the error generation circuit, generate a second plurality of trim codes utilizing a simplex algorithm based on the first error signal, and transmit the second plurality of trim codes to the circuit to be calibrated.


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