Using dual channel memory as single channel memory with command address recovery

Abstract

A technique relates to operating a memory controller. A feedback mode is initiated such that an identified memory device of first memory devices includes an identified bit lane on a data bus to be utilized for testing. A process includes sending commands on the-N bit lanes of the command address bus to a buffer and duplicating commands designated for a selected one of the-N bit lanes. The process includes sending the duplicated commands on the identified bit lane in route to the buffer, and receiving a result of a parity check for the commands sent on the-N bit lanes, such that when the result is a pass the process ends. When the result is a fail, a duplicated parity check is performed using duplicated commands on the identified bit lane in place of the selected one. When the duplicated parity check passes, the selected one is bad.