The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Nov. 17, 2017
Applicant:

Google Llc, Mountain View, CA (US);

Inventor:

Monish Shah, Dublin, CA (US);

Assignee:

Google LLC, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 12/0804 (2016.01); G06F 3/06 (2006.01); G06F 12/0868 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0611 (2013.01); G06F 3/0635 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 12/0804 (2013.01); G06F 12/0868 (2013.01); G06F 2212/214 (2013.01); G06F 2212/222 (2013.01); G06F 2212/7203 (2013.01); G06F 2212/7205 (2013.01);
Abstract

At least one aspect is directed to a NAND flash storage device including a plurality of NAND flash chips and a controller. The controller is configured to receive data over an input/output (I/O) bus and write the received data to a first NAND flash chip of the plurality of NAND flash chips and a second NAND flash chip of the plurality of NAND flash chips. The write operations to each NAND flash chip do not overlap in time. The controller is configured to read data from whichever of the first NAND flash chip or the second NAND flash chip is not currently executing a write operation such that read operations are not queued behind write operations.


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