The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Sep. 08, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Christophe Avoinne, Campbell, CA (US);

Luc Montperrus, Montigny le Bretonneux, FR;

Philippe Boucard, Le Chesnay, FR;

Rakesh Kumar Gupta, Bangalore, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/3296 (2019.01); G06F 12/0831 (2016.01); G06F 1/3287 (2019.01); G06F 1/3206 (2019.01); G06F 1/3234 (2019.01); G06F 9/54 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G06F 1/3206 (2013.01); G06F 1/3275 (2013.01); G06F 1/3287 (2013.01); G06F 9/54 (2013.01); G06F 12/0833 (2013.01); G06F 2212/1028 (2013.01); Y02D 10/13 (2018.01);
Abstract

Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.


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