The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

May. 16, 2016
Applicant:

Exascaler Inc., Chiyoda-ku, Tokyo, JP;

Inventor:

Motoaki Saito, Tokyo, JP;

Assignee:

EXASCALER INC., Chiyoda-Ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/20 (2006.01); G06F 1/18 (2006.01); H05K 7/20 (2006.01); H05K 7/02 (2006.01);
U.S. Cl.
CPC ...
G06F 1/20 (2013.01); G06F 1/18 (2013.01); H05K 7/02 (2013.01); H05K 7/20 (2013.01); H05K 7/20236 (2013.01); H05K 7/20263 (2013.01); G06F 2200/201 (2013.01);
Abstract

An electronic device, immersed in a coolant filled in a cooling apparatus, and directly cooled, is configured to be housed in a housing part of the cooling apparatus, and includes a pair of substrate groups that includes a first circuit board having at least one processor and main memories mounted onto one surface of the board, coprocessors, each having a housing with a rectangular cross-section, and an electric connection terminal, and a connector for electric connection between the first circuit board and the coprocessors. When each of the electric connection terminals of the coprocessors is inserted into the connector, a distance between the one surface of the first circuit board and a housing bottom surface of each of the coprocessors is longer than a height of the processor and each height of the main memories. The pair of substrate groups is combined while having the first circuit boards arranged at a rear surface side in a direction for reducing a distance between the one surface of the first circuit board of one of the substrate groups and a housing upper surface of each of the coprocessors of the other of the substrate groups.


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