The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Dec. 29, 2017
Applicant:

Kyland Technology Co., Ltd., Beijing, CN;

Inventors:

Zhiyong Lv, Beijing, CN;

Yi Huang, Beijing, CN;

Hao Cao, Beijing, CN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); H04L 9/06 (2006.01); H04L 9/08 (2006.01); G05B 19/418 (2006.01); G05B 15/02 (2006.01); H04B 3/54 (2006.01); G06F 13/42 (2006.01); H04L 12/40 (2006.01); H04L 12/24 (2006.01); H04L 5/00 (2006.01); H04L 29/08 (2006.01);
U.S. Cl.
CPC ...
H04L 9/06 (2013.01); G05B 15/02 (2013.01); G05B 19/4185 (2013.01); G06F 13/4291 (2013.01); H04B 3/544 (2013.01); H04L 9/0825 (2013.01); H04L 12/40032 (2013.01); H04L 41/0686 (2013.01); H04L 63/0442 (2013.01); H04L 5/0042 (2013.01); H04L 63/0428 (2013.01); H04L 67/12 (2013.01); Y02P 90/18 (2015.11);
Abstract

Disclosed are a method and apparatus for implementing security of broadband bus architecture in industrial internet field. The security of the access process can be guaranteed by encrypting data transmitted between the bus terminal and the bus controller; the operation of the entire system can be prevented from threat of abnormal data by performing security detection on the acquired data; it can be easy to treat abnormal conditions of the transport rule by the bus controller by monitoring and reporting the transport rule of the data flow over the bus by a bus terminal; and the reliability of the transmission process may be improved by interleaving the to-be-sent data at the bus controller and the bus terminal; the time delay of the data transmission resulting from the addition of the interleaving processes can also be reduced to have high transmission rate.


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